Field of the Invention
The present invention relates to the reliability of NAND-type flash memory, NOR-type flash memory, etc., and in particular it relates to an erase method of the flash memory for reducing the decreases in reliability that result from repeated writing and erasing operations.
Description of the Related Art
FIG. 1 schematically shows, in a cross section, a memory cell array of a flash memory. An N-well 12 is formed in a P-type substrate (P-sub) 10, and a P-well 14 is formed in the N-well 12. A plurality of transistors constituting NAND strings are formed in the P-well 14. Each of the NAND strings comprises a plurality of memory cells connected in series, a source-line selection transistor connected to a terminal of the memory cell, and a bit-line selection transistor connected to the other terminal of the memory cell. FIG. 1 shows a plurality of memory cell 20 connected in series, a source-line side selection transistor 22 and a bit-line side selection transistor 24. In FIG. 1, a plurality of NAND strings are formed in a row and all NAND strings in the P-well 14 constitute a block.
A source line SL is electrically connected to an n-diffusion region (source region) 23 of the source-line selection transistor 22, and a bit line BL is electrically connected to an n-diffusion region (drain region) 23 of the bit-line selection transistor 24. Moreover, a p+-diffusion region 26 for contact is formed in the P-well 14, an n+-diffusion region 27 is formed the N-well 12, and the two diffusion regions 26 and 27 are connected by virtue of a common contact 28. As described herein, erase pulses of high voltage are applied to the P-well by the common contact 28 when erasing a selected block.
FIG. 2 shows an equivalent circuit of a flash memory cell array. As shown in FIG. 2, a plurality of word lines WL1, WL2, . . . WLn are formed in the direction of the rows crossing the NAND strings. Each of the word lines WL connects the control gates of the corresponding memory cells 20 which are arranged in the row direction. Each of the selection gate-lines SGS connects the gates of the source-line selection transistors 22 which are arranged in the row direction, and each of the selection gate-lines SGD connects the gates of the bit-line selection transistors 24 which are arranged in the row direction. NAND strings are electrically connected to source lines SL when the source-line selection transistors 22 are turned on by selection gate-lines SGS. NAND strings are electrically connected to bit lines BL when the bit-line selection transistors 24 are turned on by virtue of the selection gate-lines SGD.
FIG. 3 shows voltage waveforms of nodes in an erase selection block when NAND flash memory carries out an erase operation. The Node N1 is the common contact 28 of the N-well/P-well, the node N2 is the diffusion region 23 of the source line SL for contact, the node N3 is the gate of the source-line side selection transistor 22, the node N4 is the word line (control gate) of the memory cells 20 in the same block, the node N5 is the gate of the bit-line side selection transistor 24 and the node N6 is the diffusion region of the bit-line BL for contact. Moreover, the waveform at the node N4 in a non-selected block becomes the same as those at nodes N3˜N5 in the selected block.
In NAND-type flash memory, data erasing is carried out in units of block. At this time, the voltage at the bit line of the selected block is set to zero volts (0V) or less than the voltage at the P-well 14 and a positive erase pulse is applied to the P-well 14 in which the memory cell array is formed. After applying the erase pulse Ps, the voltage of the P-well 14 returns to 0V. At this time, the voltages at nodes N2, N3, N5 and N6 are automatically boosted by virtue of capacitive coupling with the P-well 14. After erasing, it is determined whether the threshold values of the memory cells in the selected block are less than a certain value by a verification read-out. If the threshold values of all the memory cells in the block are less than the certain value, then the erase operation is completed; otherwise, if the threshold values of some of the memory cells are higher than the certain value, then the erase pulse Ps is applied again and the verification read-out is carried out (as disclosed in patent document 1).
Furthermore, to control the lower limit of the threshold value distribution of the erased memory cells, soft-programming and soft-programming verification are proposed to carry out to the erased memory cells (as disclosed in patent document 2). The flow chart is shown in FIG. 4. In FIG. 4, erase pulses Ps are applied in step S10 to erase data in the selected memory cells. Then, erase verification is carried out in step S20 to verify if the upper limit of the threshold values of the erased memory cells is below the certain value. When the erase verification is qualified, soft-programming verification is carried out in step S40 to verify if the lower limit of the threshold values of the erased memory cells is above the certain value. In step S30, soft-programming is carried out on the memory cells which are not qualified in the soft-programming verification. By using the process described above, the lower limit of the threshold value distribution is kept higher than the certain value.
On the other hand, the voltage of the P-well 14 is set to 0V and high voltages are applied to the selected word lines when a writing (programming) operation is performed. 0V and positive voltage may be applied to the bit line. When 0V is applied, the voltages at the silicon surface of the selected memory cells become 0V and electron tunneling current flows from the silicon substrate to the floating gate, whereby the threshold values of the memory cells become higher than the certain value.